Next Chapter Meeting:
Wednesday Nov 19, 2014
5:30 - 6:00 - Social time.
Attendance is free of charge to all IEEE Members and Non-Members
Please email Jim Teune (Jim.email@example.com) if you plan to attend.
Channel Modeling and Analysis for Signal Integrity in High-Speed Digital Designs
High-speed layouts on printed circuit boards for multi-gigabit signals require careful layout and analysis of the channel performance to ensure the specification for bit-error-rate is met. The physical layout of the channel is broken down into its constituent parts from transmitter to receiver including all routing geometry features. Each block in the routing is characterized in terms of S-parameters, and an end-to-end model of cascaded S-parameter blocks is assembled to model the layout. Eye patterns can then be generated from PRBS sequences and jitter can be studied. Equalization can be applied if the specified eye pattern mask is not achieved. However, breaking down layout for modeling and construction of a channel model from cross-sectional analysis for printed circuit transmission-lines, and other S-parameter blocks, is prone to errors. Small and large they can have a significant impact on the simulation results. Practical aspects of breaking up the geometry and developing models will be discussed and challenges demonstrated with examples.
James L. Drewniak
James L. Drewniak received B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Illinois at Urbana-Champaign. He is with Electromagnetic Compatibility Laboratory in the Electrical Engineering Department at Missouri University of Science and Technology (formerly University of Missouri-Rolla). His research and teaching interests include electromagnetic compatibility in high-speed digital and mixed-signal designs, signal and power integrity, electronic packaging, electromagnetic compatibility in power electronic based systems, electronics, and antenna design. He is a leader of a university research laboratory that is internationally recognized for research in EMC and signal and power integrity, with approximately 60 people, including tenured faculty, research professors, post-doctoral fellows, and over 35 graduate students. The funding for the laboratory is a balance of US government sponsors as well as industry. The Missouri S&T EMC Laboratory includes a state-of-the-art laboratory facility. A key funding component of the research is a US National Science Foundation Industry/University Research Center (I/UCRC) that is a consortium of approximately 20 companies. He is a Fellow of the IEEE, and recipient of the IEEE EMC Society's highest award for technical achievement the Richard R. Stoddart Award in 2013, a past Chair of the IEEE EMC Society technical committees TC-9 Computational EM, and TC-10 Signal Integrity, as well as a past Associate Editor of the IEEE Transactions on EMC.Click Here for .pdf map